Adverting to FIG. 1, as reductions in device scaling continue, spacing between PMOS and NMOS diffusions 101 and 103 shrinks, causing increasing leakage between NMOS diffusion 103 and N-well 105 and between PMOS diffusion 101 and P-well 107. The leakage is particularly problematic for bulk CMOS devices at the 22 nm technology node and beyond. One critical leakage path 109 occurs in the 6-Transistor SRAM cell (shown with two PMOS devices 111 and 113 and two NMOS devices 115 and 117), though similar leakage problems occur in logic devices, IO devices, and other types of circuits. In the exemplary SRAM cell, the minimum spacing between NMOS and PMOS diffusions 101 and 103 has shrunk from 80 nm to 60 nm to 46 nm for the 45 nm-node, 32 nm-node, and 22 nm-node, respectively, thereby resulting in the failure of conventional shallow trench isolation (STI) to provide adequate isolation for 22 nm-node devices or smaller. For example, as illustrated in FIG. 2, under certain conditions, the N+/P-well/N-well bipolar transistor could be turned on if the P-well/N-well junction is forward biased (shown at 201), and, therefore, causes significant leakage through a path (203) underneath the STI region 205 between NMOS 207 and PMOS 29, all on bulk p substrate 211.
One conventional technique for reducing leakage across isolation wells is to increase the doses in the base region of the parasitic bipolar transistor. By increasing the N-well and P-well doses, the base Gummel number GB increases, where
            G      B        =                  ∫        0        W            ⁢                                    n            i            2                                n            iB            2                          ⁢                                  ⁢                              N            B                                D            B                          ⁢                  ⅆ          x                      ,with ni equal to the intrinsic carrier density, niB equal to the effective intrinsic carrier density in the base of the bipolar transistor, NB equal to the base doping concentration, and DB equal to the base diffusion coefficient. Therefore, according to classic bipolar junction transistor (BJT) theory, the leakage through the parasitic BJT is suppressed. However, this method requires higher well implant doses, which increases the capacitance at the P+/N-well and N+/P-well junctions, thereby degrading the performance of the MOSFET.
Attempts have also been made to increase the STI trench depth from the conventional 225 nm to 265 nm at the critical N-well/P-well boundary. The extra 40 nm of STI leads to a wider base region of the parasitic BJT, resulting in a higher Gummel number, thereby improving isolation and reducing leakage current by 2 orders of magnitude. However, for 22 nm-node devices, the high aspect ratio (depth versus opening size) of about 6 makes the STI trench etch and fill process difficult, causing partially filled STI voids and other defects, which cause significant yield issues. For smaller devices, the aspect ratio will increase even further.
A need therefore exists for methodology enabling the formation of a CMOS device that can effectively suppress leakage current across isolation wells without etching and filling STI regions with extremely high aspect ratios, and for the resulting devices.